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Candidate
Male, 50 years, born on 5 May 1974
Yaroslavl, willing to relocate, prepared for occasional business trips
FPGA design engineer
Specializations:
- Design engineer
Employment: full time
Work schedule: full day
Work experience 20 years 4 months
January 2015 — currently
10 years 4 months
``Miatech'' LLC
FPGA design engineer
Development of videosystems for receving, processing and transmitting video information.
Used video interfaces: HDMI, FPDLink, OpenLDI, GMSL3, DisplayPort.
January 2014 — January 2015
1 year 1 month
Scientific Research Institute of Communication and Control Systems
Development team lead
Development of softaware-defined radio platform (SDR platform).
Creating the concept of a hardware and software system, developing circuit diagrams, developing
FPGA firmware, organizing and monitoring a work of a DSP programmer, a programer of embedded
January 2013 — January 2014
1 year 1 month
JSC Vega Radio Engineering Corporation
PC programmer
MCU software, a mathematician programmer of algorithms for sound and data processing, a PC programmer.
FPGA design engineer (contractor).
Lutch JSC - a part of JSC Vega Radio Engineering Corporation -------
Development of a video system that receives video information, decoding using the JPEG2000
standard and transmits it over the FiberChannel.
January 2009 — January 2013
4 years 1 month
``Garant-Plus'' LLC
FPGA design engineer
Development of a systems for capturing and analizing Ethernet traffic (100M - 1G).
Development of a system for hardware multichannels noise reduction of voice.
As part of the work on the projects cooperation with OdinTelesystems Inc., Texas, USA was carried out.
Head of section FPGA design
January 2008 — January 2009
1 year 1 month
Scientific Technical Center
FPGA design engineer
Head of section FPGA design
``Kami-Sever'' LLC -------
Leading the development team, developing and defining a concept and structure of a systems and modules, developing a FPGA firmware (modeling, verification, logic synthesis, place and route, timing analysis), developing an electrical circuit of a devices, testing and debugging prototypes.
Develompent of a system for capturing and analyzing STM (synchronous digital hierarchy) of a traffic and auxiliary information (STM - 1/4/16 levels).
January 2007 — January 2008
1 year 1 month
Scientific Technical Center
Senior FPGA design engineer
``Kami-Sever'' LLC -------
Development of an integrated system for capturing and analyzing voice traffic and auxiliary information on E1 lines (256 E1 analysis channels).
January 2005 — January 2007
2 years 1 month
Scientific Technical Center
FPGA design engineer
``Kami-Sever'' LLC -------
Development of a system for capturing and analyzing voice traffic on E1 lines (4 channels of E1 analysis).
Skills
Skill proficiency levels
About me
timing analysis, Hard-Working, Hign experience, Problem Solving, design implementation, digital sound processing, dynamic processing, micro architecture design skills, Algorithms, Data Processing, SystemVerilog, Verilog, Xilinx, Ethernet, FPGA, E1, Debugging, Bash Shell, C Programming Language, C++, DSP, Firmware, Git, IP, Linux, Matlab, Matlab Simulink model, Microsoft Windows, Python Programming, Script development, Simulink, System Architecture, Tcl/Tk, UNIX, Ubuntu, Version Control
Higher education
2005
P.G. Demidov Yaroslavl State University
Faculty of Physics
1993
college Yaroslavl
Languages
Citizenship, travel time to work
Citizenship: Russia
Permission to work: Russia
Desired travel time to work: Doesn't matter